Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
A layout file is then created using the netlist. This is accomplished through a placing and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example, in GDSII (“Graphic Data System II”) or OASIS (“Open Artwork System Interchange Standard”) formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process. One or more photomasks are created from the layout file for the photolithography of each layer. Photomasks are used to transfer the layout pattern onto the physical layer on the wafer. A photomask, or mask, provides an image of the desired physical geometries of the respective integrated circuit layer. Passing light through the mask projects the layout pattern for the layer onto the wafer. An imaging lens system projects and focuses the layout onto the substrate. The projected light pattern interacts with a photosensitive resist coating on the wafer, and resist portions that are exposed to light are rendered either soluble or insoluble in a developer solution, depending on the type of the photoresist. Accordingly, the mask pattern is transferred into the photo-resist by optical projection and chemical reactions. The photo-resist pattern is subsequently transferred to an underlying layer by an etch process. Most commonly, plasma containing chemically-selective reactive ions is used to etch high-aspect ratio trenches and holes with nearly vertical sidewalls.
With a continuing desire to provide greater functionality in smaller packages and the evolution of system-on-chip and mixed-signal designs, IC feature geometries are being driven to smaller and smaller dimensions. However, the ability to project an accurate image of increasingly smaller features onto the wafer is limited by the wavelength of the light used and the ability of the lens system. Double patterning technology (DPT) may be used to print patterns with a pitch that is tighter than can be printed with a single exposure. In DPT technology, approximately one-half the geometries of the interconnect pattern are placed on a first double patterning photomask, and the remainder of the geometries are placed on a second double patterning photomask. For example, a pattern with a 100 nanometer pitch which prints blurred when all geometries are placed on a single photo mask may be decomposed into two DPT photomasks, each with a 200 nanometer pitch which print without blurring. Geometries placed on the first DPT photomask are described as having a first color, and geometries placed on the second DPT photomask are described as having a second color.
With DPT, the design rules for the same color may differ from the design rules for dissimilar colors. Typically, the spacing requirements for lines of the same color are larger than that for lines of dissimilar colors. Unrestricted routing layout may result in “color conflicts” which violate DPT design rules. Resolving these conflicts to render a pattern DPT compatible may be computationally intensive and may also require significant re-layout of the pattern, which can significantly increase cost.
As more complicated designs are developed to achieve higher performance and higher reliability in a smaller chip area, the demands placed on routing tools increase. It is therefore desirable to have improvements in routing for integrated circuit design.